8051 MICROCONTROLLER BOOK AYALA
Ayala - The Micro Controller - Free ebook download as PDF File .pdf), Text File .txt) or read book online for free. all about microcontrollers. Ayala. *21* The Microcontroller. LUKIS and applications / Kenneth J. Ayala. p. cm. Includes index. both of whom made this book possible . The Microcontroller book. Read reviews from world's largest community for readers. Gain valuable assembly code programming knowledge with the help o.
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The Microcontroller Architecture, Programming And cittadelmonte.info architecture, programming, and applications / Kenneth J. Ayala. p. cm. Readers will be trained on programming the Intel microcontroller, one of the most integrated development software that is included at the back of the book. Search results. 14 results for Books: "Kenneth Ayala" The Microcontroller & Embedded Systems Using Assembly and C with CD. by Kenneth.
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Comparing Microprocessors and Microcontrollers The contrast between a microcontroller and a microprocessor is best exemplified by the fact that most microprocessors have many operational codes opcodes for moving data from external memory to the CPU; microcontrollers may have one, or two. Micro- processors may have one or two types of bit-handling instructions; microcontrollers will have many. To summarize. The microcontroller can function as a computer with the addition of no external digital parts; the microprocessor must have many additional parts to be operational.
To see the differences in concept between a microprocessor and a microcontroller. Note that the point here is not to show that one design is "better" than the other; the two designs are intended to be used for different purposes and in different ways. For ex- ample, the has a very rich instruction set. The penalty that is paid for this abundance is the number of multi-byte instructions needed, some 71 percent of the total number.
Each byte of a multi-byte instruction must be fetched from program memory, and each fetch takes time; this results in longer program byte counts and slower execution time versus single-byte instructions. The has a 62 percent multi-byte instruction content; the program is more compact and will run faster to accomplish similar tasks.
The disadvantage of using a "lean" instruction set as in the is increased pro- grammer effort expense to write code; this disadvantage can be overcome when writing large programs by the use of high-level languages such as BASIC and C, both of which are popular with system developers.
The price paid for reducing programmer time there is always a price is the size of the program generated. A Microcontroller Survey Markets for microcontrollers can run into millions of units per application. At these vol- umes the microcontroller is a commodity item and must be optimized so that cost is at a minimum. Semiconductor manufacturers have produced a mind-numbing array of designs that would seem to meet almost any need.
Some of the chips listed in this section are no longer in regular production, most are current, and a few are best termed "smokeware": Four-Bit Microcontrollers In a commodity chip, expense is represented more by the volume of the package and the number of pins it has than the amount of silicon inside.
To minimize pin count and pack- age size, it is necessary that the basic data word-bit count be held to a minimum, while still enabling useful intelligence to be implemented. Although 4 bits. The following table lists representative models from major manufacturers' data books. Many of these designs have been licensed to other vendors. Model Pins: FIMCS40 COP MSM TMS TLCS47 These 4-hit microcontrollers are generally intended for use in large volumes as true I -chip computers; expanding external memory, while possible, would negate the cost ad- vantage desired.
Typical applications consist of appliances and toys: Eight-Bit Microcontrollers Eight-hit microcontrollers represent a transition zone between the dedicated, high volume, 4-bit microcontrollers. Eight bits has proven to be a very useful word size for small computing tasks. Ca- pable of decimal values, or quarter-percent resolution. Most integrated circuit memo- ries and many logic functions are arranged in an 8-hit configuration that interfaces easily to data buses of 8 bits.
Application volumes for 8-bit microcontrollers may be as high as the 4-bit models, or they may be very low. Application sophistication can also range from simple appliance control to high-speed machine control and data collection.
For these reasons. The purpose of this diversity is to offer the designer a menu of similar devices that can solve almost any problem. Many times the ROM version is never used. As a further enticement for the buyer, some families have members with fewer external pins to shrink the package and the cost; others have special features such as analog-to-digital AID and digital-to-analog DIA converters on the chip.
The 8-bit arena is crowded with capable and cleverly designed contenders; this is the growth segment of the market and the manufacturers are responding vigorously to the marketplace. Each entry in the table has many variations; the total number of configurations available exceeds a total of eighty types for the eleven model numbers listed. Z Sixteen-Bit Microcontrollers Eight-bit microcontrollen can be used in a variety of applications that involve limited cal- culations and relatively simple control strategies.
As the requirement for faster response and more sophisticated calculations grows, the 8-bit designs begin to hit a limit inherent with byte-wide data words. One solution is to increase clock speeds; another is to increase the size of the data word.
Sixteen-bit microcontrollers have evolved to solve high-speed control problems of the type that might typically be confronted in the control of ser- vomechanisms, such as robot arms, or for digital signal processing DSP applications. The designs become much more focused on these types of real-time problems; some generality is lost, but the vendors still try to hit as many marketing targets as they can.
The following table lists only three contenders. Mndel Pins: H HPC The pulse width modulation PWM output is useful for controlling motor speed; it can be done using software in the 8-bit units with the usual loss of time for other tasks.
The and bit controllers have also been designed to take advantage of high- level programming languages in the expectation that very little assembly language pro- gramming will he done when employing these controllers in sophisticated applications. Thirty-Two Bit Microcontrollers Crossing the boundary from 16 to 32 bits involves more than merely doubling the word size of the computer. Software boundaries that separate dedicated programs from super- visory programs are also breached.
Thirty two bit designs target robotics, highly intelli- gent instrumentation, avionics, image processing, telecommunications, automobiles, and other environments that feature application programs running under an operating system. The line between microcomputers and microcontrollers becomes very fine here. The design emphasis now switches from on-chip features, such as RAM, ROM, timers, and serial ports, to high-speed computation features.
The following tahle provides a general list of the capability of the Intel All of the functions needed for , data communications, and timing and counting are done by adding other specialized chips. This manufacturer has dubbed all of its microcontrollers "embedded controllers," a term that seems to describe the function of the bit very well. Development Systems for Microcontrollers What is needed to be able to apply a microcontroller to your product? That is, what pack- age of hardware and software will allow the microcontroller to be programmed and con- nected to your application?
A package commonly called a "development system" is required. First, trained personnel must be available either on your technical staff or as consul- tants. One person who is versed in digital hardware and computer software is the mini- mum number. Many inexpensive EPROM programmers are sold that plug into a slot of most popular personal computers.
More expensive, and more versatile, dedicated programmers are also available. An alternative to EPROMs are vendor- supplied prototype cards that allow code to be down loaded from a host computer. Finally, software is needed, along with a personal computer to host it. The minimum software package consists of a machine language assembler.
More expensive software mainly consisting of high-level language compilers and debuggers is also available. A minimum development system, then, consists of a personal computer, a plug-in EPROM programmer, and a public-brand assembler. A more extensive system would con- sist of vendor-supplied dedicated computer systems with attendant high-level software packages and in-circuit emulators for hardware and software debugging.
Summary The fundamental differences between microprocessors and microcontrollers are: Four-bit units are pro- duced in huge volumes for very simple applications, and 8-bit units are the most versatile. Sixteen- and bit units are used in high-speed control and signal pro- cessing applications. Questions 1. Name four major differences hetween a microprocessor and a microcontroller. Explain this difference. Name 20 items that have a built-in microcontroller.
Name 10 items that should have a built-in microcontroller. Namc the most unusual application of a microcontroller that you have seen actually for sale. Name thc most likely hit size for each of the following products. Explain why ROMless versions of microcontrollers exist 8. Name two ways to speed up digital data processing 9. List three esscntial items needed to make up a dcvelopment system for programming microcontrnllers. Search the litcrature and letermine whether any manufacturer has announccd a W h i t micn controller.
Introduction The first task faced when learning to use a new computer is to become familiar with the capability of the machine. The features of the computer are best learned by studying the internal hardware design, also called the architecture of the device, to determine the type, number, and size of thc registers and other circuitry.
The hardware is manipulated by an accompanying set of program instructions, or software, which is usually studied next. Once familiar with the hardware and software, the system designer can then apply the microcontroller to the problems at hand. A natural question during this process is "What do I do with all this stuff? This chapter provides a broad overview of the architecture of the 1.
The Microcontroller - Kenneth J. Ayala - Google книги
In subsequent chapters, we will cover in greater detail the interaction between the hardware and the software. A n enhanced version o f the , the , also exists with its own family o f variations and even includes one member that can be programmed i n BASIC. This gal- axy o f parts, the result o f desires b y the manufacturers to leave no market niche unfilled, would require many chapters to cover. I n this chapter, we w i l l study a "generic" , housed i n a pin DIP, and direct the investigation o f a particular type to the data books.
The block diagram o f the i n Figure 2. The figure also shows the usual CPU components: Four register banks, each containing eight registers Sixteen bytes, which may be addressed at the bit level Eighty bytes of general-purpose data memory Thirty-two inputloutput pins arranged as four 8-bit ports: PO-P3 Two bit timerlcounters: TO and T1 Full duplex serial data receiverltransmitter: SBUF Control registers: These registers and memory locations can be made to operate using the software instructions that are incorporated as part of the design.
The program instructions have to do with the control of the registers and digital data paths that are physically contained inside the , as well as memory locations that are physically located outside the The model is complicated by the number of special-purpose registers that must be present to make a microcomputer a microcontroller.
A cursory inspection of the model is recommended for the first-time viewer; return to the model as needed while progressing through the remainder of the text. Most of the registers have a specific function; those that do occupy an individual block with a symbolic name, such as A or THO or PC.
Others, which are generally indis- tinguishable from each other, are grouped in a larger block, such as internal ROM or RAM memory. Each register, with the exception of the program counter, has an internal 1-byte ad- dress assigned to it. That is, the entire byte of data at such register addresses may be read or altered, or individual bits may be read or altered.
Software instructions are gener- ally able to specify a register by its address, its symbolic name, or both.
A pinout of the packaged in a pin DIP is shown in Figure 2. It is important to note that many of the. For this reason. Alternate functions are shown b e l o w the p o r t name in parentheses. Pin n u m - bers and pin names are shown inside the DIP package. Not all of the possible features may be used at the same time. For example, port 3 bit 0 abbreviated P3. The system designer decides which of these two functions is to be used and designs the hard- ware and software affecting that pin accordingly.
The Oscillator and Clock The heart of the is the circuitry that generates the clock pulses by which all internal operations are synchronized. Typically, a quartz crystal and capacitors are em- ployed, as shown in Figure 2. The crystal frequency is the basic internal clock fre- quency of the microcontroller. The manufacturers make available designs that can run at specified maximum and minimum frequencies, typically 1 megahertz to 16 mega- hertz.
Minimum frequencies imply that some internal memories are dynamic and must always operate above a minimum frequency, or data will be lost. Communication needs often dictate the frequency of the oscillator due to the require- ment that internal counters must divide the basic clock rate to yield standard communica- tion bit per second baud rates.
If the basic clock frequency is not divisible without a remainder. Ceramic resonators may be used as a low-cost alternative to crystal resonators. How- ever, decreases in frequency stability and accuracy make the ceramic resonator a poor choice if high-speed serial data communication with other systems, or critical timing, is to be done.
The oscillator formed by the crystal, capacitors, and an on-chip inverter generates a pulse train at the frequency of the crystal, as shown in Figure 2. The clock frequency, f. The smallest interval of time to accomplish any simple instruction, or part of a complex instruction, however, is the machine cycle.
The machine cycle is itself made up of six states. A state is the basic time interval for discrete operations of the microcontroller such as fetching an opcode byte, decoding an opcode, executing an opcode, or writing a data byte.
Two oscillator pulses define each state. Program instructions may require one, two, or four machine cycles to be executed, depending on the type of instruction. Instructions are fetched and executed by the micro- controller automatically, beginning with the instruction located at ROM memory address OOOOh at the time the microcontroller is first reset.
To calculate the time any particular instruction will take to be executed, find the num- ber of cycles, C, from the list in Appendix A. The time to execute that instruction is then found by multiplying C by 12 and dividing the product by the crystal frequency: A 12 megahertz crystal yields the con- venient time of one microsecond per cycle. An Program Counter and Data Pointer The contains two bit registers: Each is used to hold the address of a byte in memory. Program instruction bytes are fetched from locations in memory that are addressed by the PC.
The PC is automatically incremented after every instruction byte is fetched and may also be altered by certain instructions. The PC is the only register that does not have an internal address. Two of these, registers A and B, comprise the mathematical core of the central processing unit CPU.
The A accumulator register is the most versatile of the two CPU registers and is used for many operations, including addition, subtraction, integer multiplication and divi- sion, and Boolean bit manipulations. The A register is also used for all data transfers be- tween the and any external memory.
The B register is used with the A register for multiplication and division operations and has no other function other than as a location where data may be stored. Other instructions can test the condition of the flags and make decisions based upon the Rag states. In order that the flags may be conveniently addressed, they are grouped inside the program status word PSW and the power control PCON registers.
The has four math flags that respond automatically to the outcomes of math operations and three general-purpose user flags that can be set to I or cleared to 0 by the programmer as desired. Note that all of the flags can he set and cleared by the programmer at will. The math flags, however.
The program status word is shown in Figure 2. The PSW contains the math Rags, user program flag FO, and the register select bits that identify which of the four general- purpose register banks is currently in use by the program. Detailed descriptions of the math flag operations will be discussed in chapters that cover the opcodes that affect the flags. The user flags can be set or cleared using data move instructions covered in Chapter 3.
Additional memory can be added externally using suitable circuits. Unlike microcontrollers with Von Neumann architectures, which can use a single memory address for either program code or data, but not,for both, the 1 has a Harvard architecture, which uses the same address, in different memories, for code and data.
In- ternal circuitry accesses the correct memory based upon the nature of the operation in progress. Thirty-two bytes from address OOh to IFh that make up 32 working registers or- ganized as four banks of eight registers each. The four register banks are num- bered O to 3 and are made up of eight registers named RO to R7. Each register can be addressed by name when its bank is selected or by its RAM address. Thus RO of bank 3 is RO if bank 3 is currently selected or address 18h whether bank 3 is selected or not.
Register banks not selected can be used as general-purpose RAM. Bank 0 is selected upon reset. A bit-addressable area of 16 bytes occupies RAM byte addresses 20h to 2Fh, forming a total of addressable bits. An addressable bit may be specified by its bit address of OOh to 7Fh, or 8 bits may form any byte address from 20h to 2Fh.
Thus, for example, bit address 4Fh is also bit 7 of byte address 29h. Ad- dressable bits are useful when the program need only remember a binary event switch on, light off, etc. Internal RAM is in short supply as it is, so why use a byte when a bit will do?
A general-purpose RAM area above the bit area, from 30h to 7Fh, addressable as bytes. The Stack and the Stack Pointer The stack refers to an area of internal RAM that is used in conjunction with certain op- codes to store and retrieve data quickly.
The 8-bit stack pointer SP register is used by the to hold an internal RAM address that is called the "top of the stack.
When data is to be placed on the stack, the SP increments before storing data on the stack so that the stack grows up as data is stored. As data is retrieved from the stack, the byte is read from the stack, and then the S P decrements to point to the next available byte of stored data.
Operation of the stack and the SP is shown in Figure 2. The SP is set to 07h when the is reset and can be changed to any internal RAM address by the programmer. The stack is limited in height to the size of the internal RAM. The stack has the poten- tial if the programmer is not careful to limit its growth to overwrite valuable data in the register banks, bit-addressable RAM, and scratch-pad RAM areas. The programmer is responsible for making sure the stack does not grow beyond pre-defined bounds!
The stack is normally placed high in internal RAM, by an appropriate choice of the number placed in the SP register. StoringData on the Stack m Address This feature allows the programmer to change only what needs to be altered, leaving the remaining bits in that SFR unchanged. Not all o f the addresses from 80h to FFh are used for SFRs, and attempting to use an address that is not defined, or "empty," results in unpredictable results.
I n Figure 2. Failure to use this number convention will result in an assembler error when the program is assembled. Internal ROM The is organized so that data memory and program code memory can be in two entirely different physical memory entities. Each has the same address ranges. The structure of the internal RAM has been discussed previously.
Program addresses higher than OFFFh, which exceed the inter- nal ROM capacity, will cause the to automatically fetch code bytes from external program memory. As noted in Chapter I , microprocessor designs must add additional chips to interface with external circuitry; this ability is built into the microcontroller. To be commercially viable, the had to incorporate as many functions as were technically and economically feasible. The main constraint that limits numerous functions is the number of pins available to the circuit designers.
The DIP has 40 pins, and the success of the design in the marketplace was determined by the flexibility built into the use of these pins. For this reason, 24 of the pins may each be used for one of two entirely different functions, yielding a total pin configuration of The function a pin performs at any given instant depends, first, upon what is physically connected to it and, then, upon what software commands are used to "program" the pin.
Both of these factors are under the complete control of the programmer and circuit designer. Given this pin flexibility, the may be applied simply as a single component with only, or it may be expanded to include additional memory, parallel ports, and serial data communication by using the alternate pin assignments. The key to programming an alternate pin function is the port pin circuitry shown in Figure 2. Each port has a D-type output latch for each pin. For in- stance, the eight latches for port 0 are addressed at location 80h; port 0 pin 3 is bit 2 of the PO SFR.
The port latches should not be confused with the port pins; the data on the latches does not have to be the same as that on the pins. The two data paths are shown in Figure 2. The top buffer is enabled when latch data is read, and the lower buffer, when the pin state is read.
The status of each latch may be read from a latch buffer, while an input buffer is connected directly to each pin so that the pin status may be read independently of the latch state. Different opcodes access the latch or pin states as appropriate. Port operations are determined by the manner in which the is connected to external circuitry. Programmable port pins have completely different alternate functions.
The configura- tion of the control circuitry between the output latch and the port pin determines the nature of any particular port pin function. An inspection of Figure 2.
The ports are not capable of driving loads that require currents in the tens of milli- amperes mA. As previously mentioned. An example range of logic-level currents, volt- ages, and total device power requirements is given in the following table:. CMOS 2. OV 10pA mW.
These figures tell us that driving more than two LSTTL inputs degrades the noise immunity of the ports and that careful attention must be paid to buffering the ports when they must drive currents in excess of those listed.
Again, one must refer to the manufac- turers' data books when designing a "real" application. Port 0 Port 0 pins may serve as inputs. For example, when a pin is to be used as an input, a I must be written to the corresponding port 0 latch by the program, thus turn- ing both of the output transistors off, which in turn causes the pin to "float" in a high- impedance state, and the pin is essentially connected to the input buffer.
When used as an output, the pin latches that are programmed to a 0 will turn on the lower FET, grounding the pin. All latches that are programmed to a 1 still float; thus, external pullup resistors will be needed to supply a logic high when using port 0 as an output.
When port 0 is used as an address bus to external memory, internal control signals switch the address lines to the gates of the Field Effect Transistories FETs.
After the address has been formed and latched into external circuits by the Address Latch Enable ALE pulse, the bus is turned around to become a data bus. Port 0 now reads data from the external memory and must be configured as an input, so a logic 1 is automatically written by internal control logic to all port 0 latches. Port 1 Port I pins have no dual functions. Used as an input, a I is written to the latch, turning the lower FET off; the pin and the input to the pin buffer are pulled high by the FET load.
An external circuit can overcome the high impedance pullup and drive the pin low to input a 0 or leave the input high for a 1. If used as an output, the latches containing a I can drive the input of an external circuit high through the pullup. If a 0 is written to the latch, the lower FET is on, the pullup is off, and the pin can drive the input of the external circuit low. To aid in speeding up switching times when the pin is used as an output, the internal FET pullup has another FET in parallel with it.
The second FET is turned on for two oscillator time periods during a low-to-high transition on the pin, as shown in Figure 2. This arrangement provides a low impedance path to the positive voltage supply to help reduce rise times in charging any parasitic capacitances in the external circuitry. Port 2 Port 2 may be used as an inputloutput port similar in operation to port 1. The alternate use of port 2 is to supply a high-order address byte in conjunction with the port 0 low-order byte to address external memory.
Port 2 pins are momentarily changed by the address control signals when supplying the high byte of a bit address. Port 2 latches remain stable when external memory is addressed, as they do not have to be turned around set to 1 for data input as is the case for port 0.
Port 3 Port 3 is an inputloutput port similar to port I. The input and output functions can be programmed under the control of the P3 latches or under the control of various other spe- cial function registers. The port 3 alternate uses are shown in the following table: Unlike ports 0 and 2, which can have external addressing functions and change all eight port bits when in alternate use, each pin of port 3 may be individually programmed to be used either as or as one of the alternate functions.
Internal control circuitry accesses the correct physical memory, depending upon the machine cycle state and the opcode being executed. There are several reasons for adding external memory, particularly program memory, when applying the in a system. When the project is in the prototype stage, the expense-in time and money-of having a masked internal ROM made for each program "try" is prohibitive. To alleviate this problem.
8051 Microcontroller Books
The resulting circuit board layout will be identical to one that uses a factory-programmed 1. The only drawbacks to the are the specialized EPROM programmers that must be used to program the non-standard pin part, and the limit of "only" bytes of program code. The solution works well if the program will fit into 4K bytes.
Unfortunately, many times, particularly if the program is written in a high-level language, the program size exceeds 4K hytes, and an external program memory is needed.
Again, the manufac- turers provide a version for the job, the ROMless External RAM. External RAM, up to 64K bytes, may also be added to any chip in the family.
Connecting External Memory Figure 2. The accesses exter- nal RAM whenever certain program instructions are executed. Figure 2. Dur- ing any memory access cycle, port 0 is time multiplexed.
That is, it first provides the lower byte of the bit memory address, then acts as a bidirectional data bus to write or read a byte of memory data. Port 2 provides the high byte of the memory address during the entire memory readlwrite cycle. The lower address byte from port 0 must be latched into an external register to save the byte. Address byte save is accomplished by the ALE clock pulse that provides the correct timing for the ' type data latch.
The port 0 pins then become free to serve as a data bus. Port 2 A15 I I. Enable Read Write Pulse. Set when timer rolls from all ones to zero. Cleared when processor vectors to execute Interrupt service routlne located at program address Bh.
Set to 1 by program to enable timer to count; cleared to 0 by program to halt timer. Does not reset timer. Cleared when processor vectors to execute interrupt service routine located at program address Bh.
Set to 1 by program to enable tlmer to count; cleared to 0 by program to halt timer. Set to 1 when a high to low edge stgnal IS received on port 3 pin 3. Not related to timer operations. Set to 1 by program to enable external interrupt 1 to be trtggered by a falling edge signal. Set to 0 by program to enable a low level signal on external interrupt t to generate an interrupt. Set to 1 when a high to low edge signal is received on port 3 pln 3. Cleared when processor vectors to interrupt service routine located at program address h.
Not related to timer operations Continued. Note that theWR and RD signals are alternate uses for port 3 pins 16 and Also, port O is used for the lower address byte and data; port 2 is used for upper address bits. The use o f external memory consumes many o f the port pins, leaving only port I and parts o f port 3 for general Counters and Timers Many microcontroller applications require the counting o f external events, such as the frequency o f a pulse train, or the generation o f precise internal time delays between com- puter actions.
Both o f these tasks can be accomplished using software techniques, but software loops for counting or timing keep the processor occupied so that other, perhaps more important, functions are not done. To relieve the processor o f this burden, two bit up counters, named TO and T I , are provided for the general use o f the programmer.
Each counter may be programmed to count internal clock pulses. Set to 1 by program to enable external interrupt 0 to be triggered by a falling edge signal. Set to 0 by program to enable a low level signal on external interrupt 0 to generate an interrupt. Bit addressable as TCON. Cleared to 0 by program to make timer act as a timer by counting internal frequency. Setlcleared by program to select mode. A l l counter action is controlled by bit states in the timer mode control register TMOD , the timerlcounter control register TCON , and certain program instructions.
TMOD is dedicated solely to the two timers and can be considered to be two duplicate 4-bit registers, each o f which controls the action o f one o f the timers. TCON has control bits and flags for the timers in the upper nibble, and control bits and flags for the external interrupts in the lower nibble.
Timer Counter Interrupts The counters have been included on the chip to relieve the processor of timing and count- ing chores. When the program wishes to count a certain number of internal pulses or external events, a number is placed in one o f the counters. The number represents the maximum count less the desired count, plus one.
The counter increments from the initial number to the maximum and then rolls over to zero on the final pulse and also sets a timer flag. The flag condition may be tested by an instruction to tell the program that the count has been accomplished, or the flag may be used to interrupt the program.
As an example, if the crystal frequency is 6. The resultant timer clock is gated to the timer by means of the circuit shown in Figure 2.
In other words, the counter is configured as a timer, then the timer - pulses are gated to the counter hy the run bit and the gate bit or the external input bits INTX. As an example, the 6 megahertz oscillator frequency would result in a final frequency to TH of hertz. The timer flag would be set in. Pulse lnput lnterrupt Figure 2. The timer flag is also set when TLX overflows. This mode exhibits an auto-reload feature: Timer Mode 3 Timers 0 and I may be programmed to be in mode 0 , I , or 2 independently of a similar mode for the other timer.
This is not true for mode 3; the timers do not operate indepen- dently if mode 3 is chosen for timer 0. Timer 0 in mode 3 becomes two completely separate 8-bit counters. TLO is controlled by the gate arrangement of Figure 2.
Timer 1 may still be used in modes 0, 1, and 2. No interrupts will be generated by timer I while timer 0 is using the TFI overflow flag. Switching timer I to mode 3 will stop it and hold whatever count is in timer 1. Timer I can be used for baud rate generation for the serial port, or any other mode 0, 1, or 2 function that does not depend upon an interrupt or any other use of the TFI flag for proper operation.
Counting The only difference between counting and timing is the source of the clock pulses to the counters. When used as a timer, the clock pulses are sourced from the oscillator through the divide-byd circuit. When used as a counter.
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The input pulse on TX is sampled during P2 of state 5 every machine cycle. A change on the input from high to low between samples will increment the counter. Each high and low state of the input pulse must thus be held constant for at least one machine cycle to ensure reliable counting.
Since this takes 24 pulses, the maximum input frequency that can be accurately counted is the oscillator frequency divided by For our 6 megahertz crystal, the calculation yields a maximum external frequency of kilohertz. Serial Data InputIOutput Computers must he able to communicate with other computers in modern multiprocessor distributed systems. One cost-effective way to communicate is to send and receive data bits serially.
The has a serial data communication circuit that uses register SBUF to hold data. I connect to the serial data network. SBUF is physically two registers. One is write only and is used to hold data to be transmitted out of the via TXD. The other is read only and holds received data from external sources via RXD.
Both mutually exclusive registers use address 99h.
Baud rates are determined by the mode chosen. Serial Data Interrupts Serial data communication is a relatively slow process. Setlcleared by program to enable multiprocessor communications in modes 2 and 3. Clear to 0 if mode 0 is in use. Set to 1 to enable reception; cleared to 0 to dissable reception. Set to one at the end of bit 7 time in mode 0, and at the beginning of the stop bit for other modes. Must be cleared by the program. Set to one at the end of bit 7 time in mode 0, and halfway through the stop bit for other modes.
Set to 1 by program to double baud rate uslng timer 1 for modes 1, 2, and 3. Cleared to 0 by program to use timer 1 baud rate. PCON is not bit addressable. Notice that data transmission is under the complete control of the program, but reception of data is unpre- dictable and at random times that are beyond the control of the program.
These flags are ORed together to produce an interrupt to the pro- gram. The program must read these flags to determine which caused the interrupt and then clear the flag. This is unlike the timer flags that are cleared automatically; it is the respon- sibility of the programmer to write routines that handle the serial data flags.
TI is set to a I when the data has been transmitted and signifies that SBUF is empty for transmission purposes and that another data byte can be sent. If the program fails to wait for the TI Rag and overwrites SBUF while a previous data byte is in the process of being transmitted, the results will be unpredictable a polite term for "garbage out".
In addition, for mode 0 only. RI must be cleared to 0 also. Receiver interrupt Rag RI is set after data has been received in all modes. Setting REN is the only direct program control that limits the reception of unexpected data; the requirement that RI also be O for mode O prevents the reception of new data until the program has dealt with the old data and reset RI. Reception can begin in modes I , 2, and 3 if RI is set when the serial stream of bits begins.
RI must have been reset by the program before the lasr bit is received or the incoming data will be lost. Incoming data is not transferred to SBUF until the last data bit has been received so that the previous transmission can be read from SBUF while new data is being received. Serial Data Transmission Modes The 1 designers have included four modes of serial data transmission that enable data communication to be done in a variety of ways and a multitude of baud rates.
Pin TXD is connected to the internal shift frequency pulse source to supply shift pulses to external circuits. When transmitting, data is shifted out of RXD, the data changes on the falling edge of S6P2, or one clock pulse after the rising edge of the output TXD shift clock.
The sys- tem designer must design the external circuitry that receives this transmitted data to re- ceive the data reliably based on this timing. External Data Bits Shifted In. Mode 0 is intended not for data communication between computers, but as a high- speed serial data-collection method using discrete logic to achieve high data rates.
The baud rate used in mode 0 will be much higher than standard for any reasonable oscillator frequency; for a 6 megahertz crystal, the shift rate will be kilohertz.
Interrupt flag TI is set once all ten bits have been sent. Each bit interval is the inverse of the baud rate frequency, and each bit is maintained high or low over that interval. Received data is obtained in the same order; reception is triggered by the falling edge of the start bit and continues if the stop bit is true 0 level halfway through the start bit interval.
This is an anti-noise measure; if the reception circuit is triggered by noise on the transmission line, the check for a low after half a bit interval should limit false data reception. Data bits are shifted into the receiver at the programmed baud rate, and the data word will be loaded to SBUF ifthe following conditions are true: RI must be 0, and mode bit SM2 is 0 or the stop bit is I the normal state of stop bits.
RI set to 0 implies that the program has read the previous data byte and is ready to receive the next; a normal stop bit will then complete the transfer of data to SBUF regardless of the state of SM2. SM2 set to 0 enables the reception of a byte with any stop bit state, a condition which is of limited use in this mode. SM2 set to I forces reception of only "good" stop bits, an anti-noise safeguard.
RI is set to 1, indicating a new data byte has been received. If RI is found to be set at the end of the reception, indicating that the previously received data byte has not been read by the program, or if the other conditions listed are not true. Mode 1 Baud Rates Timer I is used to generate the baud rate for mode I by using the overtlow flag of the timer to determine the baud frequency. Typically, timer I is used in timer mode 2 as an autoload 8-hit timer that generates the baud frequency: The oscillator frequency is chosen to help generate both standard and nonstandard b a d rates.
If standard baud rates are desired, then an To get a standard rate of hertz then, the setting of THI may be found as follows: Both the start and stop bits are discarded. The baud rate is programmed as follows: Here, as in the case for mode 0, the baud rate is much higher than standard communica- tion rates. This high data rate is needed in many multi-processor applications. Data can be collected quickly from an extensive network of communicating microcontrollers if high baud rates are employed.
The conditions for setting RI for mode 2 are similar to mode I: RI must be 0 before the last bit is received, and SM2 must be 0 or the ninth data bit must be a I. Setting RI based upon the state of SM2 in the receiving and the state of bit 9 in the transmitted message makes multiprocessing possible by enabling some receivers to be interrupted by certain messages, while other receivers ignore those messages.
Only those 's that have SM2 set to 0 will be interrupted by received data which has the ninth data bit set too; those with SM2 set to I will not be interrupted by messages with data bit 9 at 0. All re- ceivers will be interrupted by data words that have the ninth data bit set to I; the state of SM2 will not block reception of such messages.
This scheme allows the transmitting computer to "talk" to selected receiving comput- ers without interrupting other receiving computers. Receiving computers can be com- manded by the "talker" to "listen" or "deafen" by transmitting coded byte s with the ninth data bit set to 1.
The I in data bit 9 interrupts all receivers, instructing those that are programmed to respond to the coded byte s to program the state of SM2 in their respec- tive SCON registers. Selected listeners then respond to the bit 9 set to 0 messages, while all other receivers ignore these messages. The talker can change the mix of listeners by transmitting bit 9 set to I messages that instruct new listeners to set SM2 to 0,while others are instructed to set SM2 to 1.
Serial Data Mode 3 Mode 3 is identical to mode 2 except that the baud rate is determined exactly as in mode 1, using Timer I to generate communication frequencies. Interrupts A computer program has only two ways to determine the conditions that exist in internal and external circuits. One method uses software instructions that jump on the states of flags and port pins.
The second responds to hardware signals, called interrupts, that force the program to call a sub-routine. Software techniques use up processor time that could be devoted to other tasks; interrupts take processor time only when action by the program is needed.
Set to 1 by program to enable timer 1 overflow interrupt; cleared to 0 to disable timer 1 overflow interrupt. Set to 1 by program to e n a b l e m interrupt; cleared to O to disable interrupt. Set to 1 by program to e n a b l e m interrupt; cleared to 0 to disable interrupt. Interrupts may be generated by internal chip operations or provided by external sources. Any interrupt can cause the to perform a hardware call to an interrupt- handling subroutine that is located at a predetermined by the designers absolute address in program memory.
Five interrupts are provided in the Three of these are generated automatically by internal operations: Two interrupts are triggered by external signals provided by circuitry that is connected to pins rn and port pins P3. All interrupt functions are under the control of the program.
The programmer is able to alter control bits in the interrupt enable register IE , the intempt priority register lP , and the timer control register TCON. The program can block all or any combination of the interrupts from acting on the program by suitably setting or clearing bits in these regis- ters. After the interrupt has been handled by the interrupt subroutine, which is placed by the programmer at the interrupt location in program memory, the interrupted program must resume operation at the instruction where the interrupt took place.
The PC address will be restored from the stack after an RETl instruction is executed at the end of the interrupt subroutine.
The flag is cleared to 0 when the resulting interrupt generates a program call to the appro- priate timer subroutine in memory. These are ORed together to provide a single interrupt to the processor: These bits are not cleared when the interrupt-generated program call is made by the processor. The program that handles serial data communication must reset RI or TI to 0 to enable the next data communication operation. External Interrupts Pins and are used by external circuitry.
The IEX flags may be set when the m p i n signal r e a c h e s low level, or the flags may be set when a high-to-low transition takes place on the INTX pin.
Flags IEX will be reset when a transition-generated interrupt is accepted by the pro- cessor and the interrupt subroutine is accessed. It is the responsibility of the system de- signer and programmer to reset any level-generated external interrupts when they are serviced by the program. The external circuit musr remove the low level before an RETI is executed. Failure to remove the low will result in an immediate interrupt after RETI, from the same source. Reset A reset can be considered to be the ultimate interrupt because the program may not block the action of the voltage on the RST pin.
This type of interrupt is often called "non- maskable," since no combination of bits in any register can stop, or mask the reset action. Unlike other interrupts, the PC is not stored for later program resumption; a reset is an absolute command to jump to program address OOOOh and commence running from there. Whenever a high level is applied to the RST pin, the enters a reset condition.
After the RST pin is brought low, the internal registers will have the values shown in the following table:. Internal RAM is not changed by a reset; however, the states of the internal RAM when power is first applied to the 1 are random. Register bank 0 is selected upon reset as all hits in PSW are 0. The IE register holds the program- mable bits that can enable or disable all the interrupts as a group, or if the group is en- abled, each individual interrupt source can be enabled or disabled.
Often, it is desirable to be able to set priorities among competing interrupts that may conceivably occur simultaneously. The IP register bits may be set by the program to assign priorities among the various interrupt sources so that more important interrupts can be serviced first should two or more interrupts occur at the same time. Bit EA is a master, or "global," bit that can enable or disable all of the interrupts.
Bits set to 1 give the accompanying interrupt a high priority while a 0 assigns a low priority. Interrupts with a high priority can interrupt another interrupt with a lower priority: If two interrupts with the same priority occur at the same time, then they have the following ranking: IEO 2.
TFO 3. IEl 4. TFI 5. Interrupt Destinations Each interrupt source causes the program to do a hardware call to one of the dedicated addresses in program memory.
It is the responsibility of the programmer to place a routine at the address that will service the interrupt. The interrupt saves the PC of the program, which is running at the time the interrupt is serviced on the stack in internal RAM.
A call is then done to the appropriate memory location. These locations are shown in the following table: A RETI instruction at the end of the routine restores the PC to its place in the inter- rupted program and resets the interrupt logic so that another interrupt can be serviced.
Interrupts that occur but are ignored due to any blocking condition IE bit not set or a higher priority interrupt already in process must persist until they are serviced, or they will be lost.
This requirement applies primarily to the level-activated tNTX interrupts. Software Generated Interrupts When any interrupt flag is set to I by any means, an interrupt is generated unless blocked. This means that the program itself can cause interrupts of any kind to be generated simply by setting the desired interrupt flag to I using a program instruction. Summary The internal hardware configuration of the registers and control circuits have been examined at the functional block diagram level.
The 1 may be considered to be a col- lection of RAM, ROM, and addressable registers that have some unique functions. Questions Find the following using the information provided i n Chapter 2. Size of the internal RAM. Internal ROM size in the Execution time o f a single byte instruction for a 6 megahertz crystal.
The bit data addressing registers and their functions. Registers that can do division. The flags that are stored i n the PSW.
Which register holds the serial data interrupt bits T I and RI. Address of the stack when the is reset. Number of register banks and their addresses. Ports used for external memory access. Address of a subroutine that handles a timer I interrupt. Why a low-address byte latch for external memory is needed.
How an pin can be both an input and output. Which port has no alternate functions. The maximum pulse rate that can be counted on pin TI if the oscillator frequency is 6 megahertz. Which bits in which registers must be set to give the serial data intempt the highest priority.
The baud rate for the serial port in mode 0 for a 6 megahertz crystal. The largest possible time delay for a timer in mode 1 if a 6 megahertz crystal is used. The setting of THl. Find the setting for both values of SMOD. The address of the PCON special-function register. The time it will take a timer in mode I to overflow if initially set to 03AEh with a 6 megahertz crystal.
Which bits in which registen must be set to I to have timer 0 count input pulses on pin TO in timer mode 0.
The signal that reads external ROM. When used in rnultipmcessing, which bit in which register is used by a transmitting to signal receiving 's that an interrupt should be generated. The two conditions under which program opcodes are fetched from external, rather than internal, memory. Which bits in which register s must be set to m a k e r n level activated. The address of the interrupt program for the level-generated interrupt. The bit address of bit 4 of RAM byte 2Ah.
Moving Data. Introduction A computer typically spends more time moving data from one location to another than it spends on any other operation. It is not surprising, therefore, to find that more instructions are provided for moving data than for any other type of operation. Data is stored at a source address and moved actually, the data is copied to a desti- nation address. The ways by which these addresses are specified are called the addressing modes.
The mnemonics are written with the destination address named first, fol- lowed by the source address. A detailed study of the operational codes opcodes of the 1 begins in this chapter.
Although there are 28 distinct mnemonics that copy data from a source to a destination, they may be divided into the following three main types: MOV destination, source 2. XCH destination, source The following four addressing modes are used to access data: Immediate addressing mode 2. Direct addressing mode 4. Indirect addressing mode The MOV opcodes involve data transfers within the 1 memory.
This memory is divided into the following four distinct physical parts: Internal RAM 2. Internal special-function registers 3. External RAM 4. Internal and external ROM Finally, the following five types of opcodes are used to move data: MOV 2.
Packaged with a customized disk containing an assembler and simulator. Focuses on programming the Intel microcontroller, one of the most common microprocessors used in controls or instrumentation applications using assembly code.
Text has been updated to include easier-to-read computer programs and more hardware interfacing. Instruction Set in the Appendix has been expanded. Preliminary and hardware chapters from Ayala's text have been added so the text can now be used in a first microprocessor course as well as advanced. Convert currency. Add to Basket.
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